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W949D6CB / W949D2CB
512Mb Mobile LPDDR
During Read bursts, DQS is driven by the LPDDR SDRAM along with the output data. The initial Low state of the
DQS is known as the read preamble; the Low state coincident with last data-out element is known as the read post-
amble. The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out
elements are edge aligned to successive edges of DQS. This is shown in following figure with a CAS latency of 2
and 3.
Upon completion of a read burst, assuming no other READ command has been initiated, the DQs will go to High-Z.
7.5.3 Read Burst Showing CAS Latency
CK
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
Address
BA Col n
CL=2
DQS
DQ
DO n
CL=3
DQS
DQ
1)DO n=Data Out from column n
DO n
= Don't Care
2)BA,Col n =Bank A,Column n
3)Burst Length=4;3 subsequent elements of Data Out appear inthe programmed order following DO n
4)Shown with nominal tAC, tDQSCK and tDQSQ
7.5.4 Read to Read
Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is
being truncated. The new READ command should be issued X cycles after the first READ command, where X
equals the number of desired data-out element pairs (pairs are required by the 2n-prefetch architecture). This is
shown in following figure.
Publication Release Date: Sep, 21, 2011
- 29 -
Revision A01-007
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